Optimization of Partial Products in Low Power Baugh Wooley Multiplier using Modified Shannon Adder Cell for Efficient ALU Design Prabhu B. M.*, Dr. Padma S.** *Assistant Professor, Electrical and Electronics Engineering, Angel college of Engineering and Technology, Tirupur, India. bmprabhu16@gmail.com **Professor, Electrical and Electronics Engineering, Sona college of Technology, Salem, India Online published on 23 March, 2017. Abstract This paper presents the design of low power digital multiplier. The basic objective to perform a repeated addition, while the repeated addition processing we can get a multiplier and the performance behavior of any processor or controller will be depend upon its power, speed and area. So the power, speed and area should be optimized in order to get an effective architecture for processor or controller. Each and every processor unit has ALU (Arithmetic logic units). That arithmetic function includes Addition, Subtraction, Multiplication, Division, shifter and many manipulation units. Multiplication is one of the important functions in arithmetic operations, and it is more complex unit to develop the next level of bits. To understand the proposed multiplier exhibiting low power operation the theoretical analyzing switching activates of partial products are derived. Based on the partial product evaluation the simulation is performed for various multipliers. This multiplier is also used in DSP application, measurements, filters, communication, Image processing, Robotics, Intelligence of embedded systems etc., The multiplier circuits are schematized and their layouts are design and generated by using Tanner T-SPICE CAD tools. Top Keywords Adder, multipliers, power consumptions, switching activities. Top |