Performance Analysis of 11-Multilevel Inverters using Sinusoidal PWM Techniques with Reduced Switching Pattern Lakshmikhandan K.*, Dr. Srinivasan Andy**, Dharani M.*** *Research Scholar, Anna University, Chennai, India. klkhandan@gmail.com **Professor, Valliammai Engineering College, Chennai, Tamilnadu, India. itzsrini@yahoo.co.in ***Assistant Professor, Adhiparasakthi College of Engineering, India. dharanikhandan@gmail.com Online published on 23 March, 2017. Abstract To provide power quality, eradication of the harmonic becomes indispensably necessary. In our analysis, sinusoidal pulse width modulation techniques with reduced switching pattern is proposed which can minimize the total harmonic distortion and enhance the output level voltages in eleven-level inverters. In this paper the main objective is the useof less number of switches which are compared with existing topology, where it can reduces the complexity, overall size of the system. Under the steady-state condition, 11-level cascaded multi level inverter are suitable for high and medium power applications. This proposed 11-level inverter has been validated using MATLAB software and by hardware implementation. Top Keywords Multilevel inverter, Cascaded multilevel inverter, Total Harmonic Distortion (THD), Pulse width modulation, Switches. Top |