Reduction of Gate Power Dissipation in Zigbee SOC using Power Gating Logic Parthiban K.*, Sasikumar S.** *Faculty, Electronics and Communication Engineering, Imayam College of Engineering, Thuraiyur, India **Faculty, Electronics and Communication Engineering, CMS College of Engineering, Namakkal, India Online published on 2 August, 2016. Abstract Zigbee system-on-chip (SoC) is an essential module in all advanced wireless devices and it is the alternating advanced technology over the conventional bluetooth technology. The gate power dissipation is high in conventional Zigbee SoC. In this paper, the power gating technique is proposed with retention logic inorder to reduce the leakage current in standby mode of Zigbee SoC. The proposed circuit is designed and simulated using TANNER tool. The performance of the proposed methodology is compared with conventional techniques interms of power consumption and average delay. Top Keywords Zigbee SoC, bluetooth, gate power dissipation, leakage current, average delay. Top |