Users online: 1626    [ij] [ij] [ij] 
Email id

INROADS- An International Journal of Jaipur National University
Year : 2016, Volume : 5, Issue : 1s
First page : ( 245) Last page : ( 249)
Print ISSN : 2277-4904. Online ISSN : 2277-4912.
Article DOI : 10.5958/2277-4912.2016.00047.3

Comparative Analysis of Leakage Reduction Techniques in Voltage Mode and Current Latch Sense Amplifiers in Sram Cell

Shrivastava Smarika*, Tomar Vinay Kumar**

Department of ECE, IET, GLA University, Mathura, (U.P.), India

*Email id: smarika.shrivastava12@gmail.com

** vinay.tomar@gla.ac.in

Online published on 2 August, 2016.


In present paper, the comparative analysis of different type of low power reduction techniques has been performed by implementing in voltage mode and current latch sense amplifier 6-T SRAM cell. The low power reduction techniques have been realized in 6-T SRAM sense amplifiers using the 90-nm 1-V CMOS technologies. Total power dissipation of current latch sense amplifier is 14 μw which is 41.59 percent less than the voltage mode sense amplifier. It has been found that Sleep transistor technique is very effective to reduce leakage power as well as total power dissipation in voltage mode sense amplifier. However, this technique is not so efficient to reduce total power dissipation in current latch sense amplifier. Furthermore, it has been observed that Dual Sleep method is more effective to reduce total power dissipation in current latch sense amplifier.



Senseamplifier, Leakagepower dissipation, CLSA(currentlatchsenseamplifier), VMSA(voltagemode sense amplifier).


║ Site map ║ Privacy Policy ║ Copyright ║ Terms & Conditions ║ Page Rank Tool
330,917,752 visitor(s) since 30th May, 2005.
All rights reserved. Site designed and maintained by DIVA ENTERPRISES PVT. LTD..
Note: Please use Internet Explorer (6.0 or above). Some functionalities may not work in other browsers.