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Indian Journal of Public Health Research & Development
Year : 2019, Volume : 10, Issue : 5
First page : ( 921) Last page : ( 927)
Print ISSN : 0976-0245. Online ISSN : 0976-5506.
Article DOI : 10.5958/0976-5506.2019.01197.5

Design and Analysis of Low Power VCO Enabled Quantizer for CT Sigma Delta ADC

Shreyas H S1, Chavan Arunkumar P1, Aradhya H V Ravish1

1Department of ECE, R. V. College Engineering, Bangalore, India

Online published on 4 June, 2019.


This paper presents design and analysis of low power Voltage Controlled Oscillator (VCO) enabled quantizer in Continuous Time (CT) Sigma Delta Analog to Digital converter (ADC) using 180nm CMOS technology using Cadence Virtuoso Tool. The VCO based quantizer in Σ-Δ ADC includes loop filter, VCO quantizer and 3-bit feedback Digital to Analog Converter (DAC). The basic building block of loop filter is Operational Amplifier (OP-AMP). The two stage OP-AMP designed offers 61.51 dB gain with the unity gain bandwidth of 30.59MHz. The keystone of the ADC is VCO based qauntizer clocked at 27.34MHz, which obtains fourth order noise shaping of its quantization noise. A low power VCO is designed using seven stage ring oscillator and Logic Structure Reduction Flip Flop (LRFF) based D-Flip Flop. The VCO based qauntizer with CT Σ-Δ ADC consumes a power of 2.57 m W with a supply voltage of 1.8V.



Continuous time(CT) Sigma delta Analog to Digital converter(ADC), Operational Amplifier (OP-AMP), low power Logic structure Reduction Flip flop (LRFF).


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